Functional Verification

Whitepapers, case studies and other useful ponderings on verification methodologies.

Verification IP Qualification and Usage Methodology for SoC Design

-- Michael Horne

Using SystemVerilog Now with DPI

-- Edelman, Warmke

Guidelines for SystemVerilog Assertion IP Development

-- Cerny, Bergeron, Thottasseri, Anderson

The Role of Functional Coverage in Verifying the Infineon C166S IP

-- Andrew Betts

Driving Reset on the Specman Highway: Rules of the Road

-- Chris Macionski

Case Study: Using a High Level Verification Language for a successful validation of the Infineon C166S Microcontroller

-- Celia Clause

Shotgun Verification, or The Homer Simpson Guide to Verification

-- Peet James

Signal Mapping in Specman e

-- Hans van der Schoot

Portable Automatic In-Situ Testbench Generation

-- Janick Bergeron, Chuck Mangan, Lewis Sternberg

Shotgun e An Eight-Step Approach to Experience Random Verification

-- Peet James, Chris Macionski

Random Generation Tutorial

-- Peet James

VHDL Verification Partitioning with Verilog-Like Flexibility

-- Dan Pietroske

Exploiting the Power of Vera: Creating Useful Class Libraries

-- Janick Bergeron

Avoiding Verilog Nightmares During Verification

-- David Black, Lewis Sternberg

VHDL Verification Partitioning with Verilog-Like Flexibility

-- Dan Pietroske

Vera, Vera on the Wall, Useful Lessons for First-Time Vera Users

-- Peet James

A Computer Model for Training in Design Reuse

-- Andrew Betts, Michael Keating

The Five-Day Verification Plan

-- Peet James

Cisco Hypertransport eVC

-- Sean Smith, Cisco Systems

A Unified Functional Verification Approach for Mixed Analog-Digital ASIC Designs

-- Bill Luo, Jim Lear, Legerity, Inc.

Designing Verification Flows Using Specman Elite

-- Bryan Morris, Nortel Networks

Case Study: Functional Covererage using Specman Elite

-- Mike Thompson, Tundra Semiconductor

Getting It Right: AMS Design and Verification Strategies

-- Lewis Sternberg

EDA Articles

Noteworthy articles and case studies from EDA companies and leading technical journals and papers

It's About Time -- Making the Case for Unified Verification

-- EE Design, Cadence Design

Verification Reuse Assures Predictable Design

-- ISD Magazine

Verification Reuse Offers Real Benefits

-- EE Design, Verisity Design

Whitepaper: Verification Reuse Methodology

-- Cadence

Using Specman Elite to Verify a 6-Port Switch ASIC

-- Paradigm Works

Integrating Third-Party Tools into Verisity's Specman Elite

-- Paradigm Works

Analysis of SoC Design Costs

-- International Business Strategies, Synopsys

Simulation Performance

Auditing your Design to Reduce Random Testing Needs

-- Dan Joyce, Raymond Harlan, Ramon Enriquez

Speeding up Verilog 10x-100x

-- Rajesh Bawankule, Cisco Systems

Speeding up ModelSim Run Times

-- Joe Rodriguez, Mentor Graphics

Managing VHDL Models with Makefiles

-- Janick Bergeron

Design Rules for Stable, Reliable Synchronous Systems

-- Peter Chambers

Design & Synthesis

Using SystemVerilog Now with DPI

-- Edelman, Warmke

Working with Behavioral Compiler: Some Helpful Tips

-- David Black

9 Area Reduction Tricks Using Synopsys DC

-- Synopsys

Steve Golson's Favorite dc_shell Tricks

-- Steve Golson