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Online Specman and
e Tutorial
Want to bone up on Specman and
the e language in a hurry? Check out Avidan Efody's
valuable online Tutorial and collection of coding and
methodology tips.
Process for qualifying
Verification IP
Looking for quality Verification
IP for your next SoC or FPGA design? Wondering how you
can separate the shoddy from the spectacular? Check
out Michael Horne's DVCon '05 paper on VIP qualification and
usage methods for a step-by-step qualification process that
will save you time and headaches.
Using the
SystemVerilog Direct Programming Interface
Check out this cool primer by
Edelman and Warmke on DPI programming and learn how to hook
up your C-models to SystemVerilog. Presented at DVCon
2005.
Guidelines for
developing SystemVerilog Assertion IP
Four engineers from Synopsys
share their insight into developing Assertion IP using
SystemVerilog in this informative whitepaper from DVCon '05.
Online Verilog
mini-course
Need a quick primer on Verilog?
Want a no-fuss overview of the language? Chris Macionski
reviews a useful 9-section, free online course from two of the
best known Verilog experts in the industry.
Verifica picks 4 top
verification reference texts
From Janick's "Writing
Testbenches" to Peet James' "Verification Plans", we give you
our opinion on the top 4 texts all verification engineers
should have in their reference library.
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