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Random-based Verification:
A Methodology Primer

Course duration: 1 day

Course Curriculum.

This one-day methodology primer shows gives you a solid introduction to random-based verification methodologies using HVL-based languages like Verisity's Specman Elite, Synopsys' VERA, and SystemVerilog.  The perfect introduction for design and verification teams considering a move to random-based methodologies for complex ASIC, FPGA and board-level design verification, our experienced Verification Methodology Consultants will help guide you through the whys and hows of random test generation, data checking strategies, and functional coverage to increase your verification confidence and productivity.  In this intense, focused course you will learn:

  1.

Introduction to random-based methodologies helps you understand the rationale for using random-based techniques for verifying today's complex systems.  We define what "verification" really means, examine traditional methods vs. random-based methods, review white-box verification, and explain the role of object-oriented programming in modern verification methods. Finally we review the importance of reusable verification IP, and summarize the key advantages of HVLs over Verilog and VHDL.
2.

The 3 key areas of random verification are explored in depth.  First we explore efficient test generation, reviewing basic, random and directed generation methods, discuss how generation modules can be extended and constrained, define sequences and scenarios, and review how to manage generation repeatability.  Next, we explore data checking methods and the role (and how to setup) scoreboards.  Finally, we explain what functional coverage is, how to set reasonable coverage goals, and how to write functional coverage while maintaining simulation performance. 

  3.

The role of the Verification Plan offers a critical look at the importance of driving your random-based methodology from a succinct Verification Plan (VP).  We explain the rationale for the VP, common misunderstandings of what a VP is, and explain the spiral process for creating an efficient VP.  We discuss the different aspect-oriented verification methods based on interface, feature, and corner approaches, as well as DFV and directed testcase approaches.  We close the session with an in-depth group exercise on creating a working, efficient VP.

Who should attend?

If you are considering a shift in your verification methodology from traditional, directed test methods to new, modern random-based approaches, then this course is for you.  Engineers and teams considering the adoption of Verisity Specman Elite, Synopsys VERA, or SystemVerilog should attend this course to ensure a clear understanding of what random-based methods (and tools) can do for you.

The learning environment.

This is an interactive course with group exercises that cement the concepts taught in the lecture portion of each session.  The instructor can provide on-the-fly review of how to use Specman and VERA tools for random-verification, including review snippets from our core random-based methodology training classes.

How to attend this course.

You can attend a regularly scheduled public course, or schedule your own private session at your facility.  To find out more, contact us toll free now at , or contact us by Clicking Here.

Detailed course outline.

This course is structured as multiple sessions taught over a 6 to 8 hour period. Interactive labs and group exercises are distributed throughout the course. For more information about course content and structure, or if you're interested in customization, please call us toll free at , or contact us by Clicking Here.

 

Section 1:

Introduction to Random-Based Methods
 

What is design verification?  Review of verification, non-verification. Evaluating possible verification outcomes.
 

Traditional (Verilog, VHDL) directed methods for verifying.  How random-based methods compare to traditional methods.
 

Handling verification granularity -- what's the proper level to verify? System? Block? Core?
 

A review of black-box, white-box, grey-box testing methods.
 

The role of object-oriented programming in HVLs
 

Reusable verification IP and how to accelerated overall system verification.
 

Understanding the key productivity points for HVLs over Verilog and VHDL.
     
 

Section 2:

The 3 Key Areas of Random Verification
 

Reviewing test generation methods
 

 

  • Data generation flow

  • Principal generation methods: basic, directed, random, constrained-random

  • Handling generation repeatability

  • How generation blocks are extended

  • Constraining blocks for managing random characteristics

  • The role of sequences and scenarios
 

ABCs of data checking
 

 

  • What is data checking?

  • Scoreboards and tracking results

  • Temporal checks

  • How to use events for data checking
 

Functional coverage explained
 

 

  • Defining coverage goals

  • What is functional coverage?

  • Using functional coverage to explore which tests are most effective, redundant, where the test holes are,

  • Basic, transition, cross coverage types

  • Measuring coverage: knowing when you're "done"
     
 

Section 3:

The Role of the Verification Plan
 

What is a Verification Plan (VP)?
 

How VPs are created; issues of ownership and format; common mistakes in VP structure.
 

The spiral process for creating a VP.  Hardware phases, verification phases, random with phases.
 

Addressing on-the fly and post-processing self-check strategies
 

Different aspect approaches to verification, including interface-based, feature-based, corner-based.  Design for Verification approaches, directed testcases, and the configuration generator approach.
 

Group Exercise: Developing an efficient, working VP
   
  • Overview of the challenge
  • Managing a "Spec Dump"
  • The Verification Infrastructure diagram
  • Managing layers, phases, aspects
  • Wrapping it up
     

Schedule your Verifica course today.

There is no substitute for a private course taught on-site at your facility, particularly when you have 6 or more engineers to train. Simply put, for large groups it’s always less expensive for us to come to you than the other way around. And if you want a custom course, we can arrange it. Do you need to squeeze a four day course into three? No problem. We know how to do it without compromise. And if you need a course on short notice, we can be there sooner than you think. For more information, contact us at:

Verifica – the right kind of verification training, tuned to your needs.  Contact us now.