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Advanced Verification Methods Using
Specman EliteTM
Including Verisity eRMTM

Course duration: 3 days

Course Curriculum.

This three-day interactive course teaches you how to overcome the "white page syndrome" – Now that you know e and Verisity’s Specman Elite, what’s next?  In this class, you will go through the step-by-step process required to plan and implement a sophisticated, self-checking verification environment for first-time success.

The course is rich in methodology hints and tricks used by our verification experts who regularly verify 10+ million gate systems – experts with knowledge that only comes from being the independent voice in the EDA verification industry.  With the help and guidance of our experienced Specman verification consultants, you will learn:

  1.

Jump Start e review refreshes your mind about key concepts in using e and Verisity’s Specman Elite to verify your designs. This review reminds you about important e concepts, reiterates helpful tips and methodology you may have overlooked, and ensures everyone is familiar with the elements that are used throughout the course.

2.

Bus functional models are the cornerstone of a proper high-level verification process. When properly designed, they can be highly reusable and configurable. In addition to verifying functions, bus-functional models can verify the timing of output signal timing. This verification can be decoupled from the functional verification to improve simulation performance.

  3.

Verification plan development first demonstrates how random, constrained testing can be more productive than a traditional, directed testing approach. Next, the role of functional coverage as a constrained-random approach is explored. Lastly, the verification plan needs to use a different approach than a plan designed for a directed approach. A process for defining a suitable verification plan is defined.

  4.

Verification environment details how to implement the appropriate constrainable, random environment structure for the verification strategy you have outlined.

  5.

Simulation management explains how the simulations are carried out. Configuration management, directory structure and scripts are discussed. The merits of using compiled e code and using tracing and logging are explained.

  6.

Data modeling helps you understand how to model data objects. Object-oriented thinking is presented in the verification context and example data structures are discussed. Implementation techniques for properly translating high-level data types to physical levels are demonstrated. This section concludes with detailed explanations on techniques to improve run-time performance.

  7.

Random generation involves more than calling a random number generator function. Random generation must be properly designed to offer the proper level of controllability over all significant parameters, while minimizing the modifications necessary to add or tune constraints. Random generation can also be used to inject errors or protocol violations in bus-functional models.

  8.

Self-checking strategies usually involve using scoreboarding techniques. Creating a scoreboard and adding information to optimize performance is explored.

  9.

Functional coverage answers the question of how much work is left? This section explores in detail what needs to be verified and when to do it.

Who should attend?

If you need to verify a design with a high-degree of confidence, implement testbenches creating reusable verification components, minimize code development effort, increase productivity and have little or some prior knowledge of the fundamentals of e or Specman Elite, then this course is for you.

Prerequisites for this class.

Successful completion of Verifica’s course Introduction to Specman Elite Verification Methods or equivalent experience with Specman.

The learning environment.

This is an interactive course with numerous labs that cement the concepts taught in the lecture portion of each session. Students will use the latest version of Verisity’s Specman Elite.

This class can be taught using either Verilog or VHDL as the design language. You can sign-up for or request a class that uses the HDL you prefer, although little reference is made to the HDL model – part of the power of Specman Elite.

How to attend this course.

You can attend a regularly scheduled public course, or schedule your own private session at your facility.  To find out more, contact us toll free now at , or contact us by Clicking Here.

Detailed course outline.

This course is structured as multiple sessions taught over three days. Interactive labs and group exercises are distributed throughout the course. For more information about course content and structure, or if you're interested in customization, please call us toll free at , or contact us by Clicking Here.

 

Section 1:

Jump Start e Language Refresher

 

Struct and Units. Use and predefined.

 

Pre-run and run-time generation.

 

Temporal expressions.

 

Functional coverage.

 

Lab Session

     
 

Section 2:

Bus-Functional Models

 

Implementing bus-functional models in Specman Elite.

 

Making bus-functional models reusable and portable.

 

Bus-functional model usage models.

 

Lab Session

     
 

Section 3:

The Verification Plan

 

Traditional vs. Random.

 

Functional coverage as a feedback mechanism.

 

Defining functional coverage elements.

 

Verification environment basic elements.

 

Group Exercise

     
 

Section 4:

The Verification Environment

 

Granularity of verification: block level vs. system level.

 

Black, white and grey boxes.

 

Verification environment structure. BFMs, Generators, monitors, scoreboards and the test harness.

 

Verification run structure.

 

Termination conditions.

 

 Resetting a simulation.

 

Lab Session

     
 

Section 5:

Simulation Management

 

Configuration management. File names. Directory structure.

 

Importing files.

 

Runs scripts. Coverage. Seeds. Saving/restore state.

 

Compiled code.

 

Tracing and logging.

 

Lab Session

     
 

Section 6:

Data Modeling

 

Object Oriented (OO) thinking

 

Example data stuctures. Configuration descriptor. Packets.

 

Fields. Physical. Virtual. Derived.

 

When extensions. Packing.

 

Virtual methods.

 

Lab Session

     
 

Section 7:

Random Generation

 

Planning constrainability.

 

Planning for independent streams.

 

Lab Session

 

Random scenarios.

 

Scenario implementation and generation. DUT feedback.

 

Debugging contradictions.

 

Lab Session

     
 

Section 8:

Self-checking Strategies

 

Scoreboarding. Definition. Use.

 

Scoreboard optimization.

 

Lab Session

     
 

Section 9:

Functional Coverage

 

Defining when. Feature based. Race conditions.

 

Defining what. Proper level. Cross coverage.

 

Statistics. Use of illegal.

 

Holes. Goals. Grading.

 

Buckets. Minimizing memory usage.

 

Lab Session

     

Schedule your Verifica course today.

There is no substitute for a private course taught on-site at your facility, particularly when you have 6 or more engineers to train. Simply put, for large groups it’s always less expensive for us to come to you than the other way around. And if you want a custom course, we can arrange it. Do you need to squeeze a four day course into three? No problem. We know how to do it without compromise. And if you need a course on short notice, we can be there sooner than you think. For more information, contact us at:

Verifica – the right kind of verification training, tuned to your needs.  Contact us now.