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Course duration: 1 day
This one-day
methodology primer shows you how
coverage is used in a modern random-based verification
environment to verify your complex ASIC, FPGA, and board-level
designs. Written specifically for Verisity Specman e
based environments, our experienced Verification Methodology
Consultants will help guide you through the whys and hows of
writing functional coverage tests to increase your
verification confidence and productivity. In this
intense, focused course you will learn:
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1. |
Random-based Verification Coverage overview
helps you understand the rationale for using
random-based techniques for verifying today's complex
systems, including comparing traditional directed
approaches with today's random methods, and how data
checking is performed. We then zero-in on the key
reasons why these new techniques raise verification
productivity. We also introduce you to the basics
of Verisity's Specman Elite environment for those newly
exposed to the tool. |
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The Verification Plan is the focal point for
defining exactly what needs to be tested, and drives the
coverage criteria. In this section, we introduce
you to the verification plan (VP) key parts and how to
write one. We then discuss the key layers and
phases of implementing the VP, error detections
strategies, and 7 principal approaches you're likely to
use. |
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Functional coverage: how it works
is reviewed in this section, including determining what
should be covered, how to set attainable coverage goals,
and exactly how Specman handles functional coverage.
A group exercise cements your knowledge on how
functional coverage works and why it is critical to your
verification success. |
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Functional Coverage: basic syntax
explains much of the gritty detail on how coverage tests
are written, reviewing coverage groups, basic, cross and
transition coverage items, how to extend coverage
groups, coverage configuration, coverage IO commands,
and displaying coverage data. An in-depth
individual lab session gives you hands-on experience
writing coverage. |
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Functional Coverage: when and what
explains how to implement coverage via extensions, and
how to think in terms of what to cover and
when to cover. We explain in detail the
concept of coverage buckets, coverage reporting, and
coverage grading. A lab session brings the day's
concepts full-circle. |
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6. |
Coverage Concerns
reviews some of the issues you will face in real-world
verification projects using coverage, including
addressing verification performance issues, data
overloading, memory usage issues, and incremental
coverage. We close this section with an example
case study showing how coverage problems and solutions
can be very design dependent. Finally, we review
the day's concepts and give you and your team an
opportunity to review your verification issues with the
Instructor. |
If you need
to write coverage in e for your current verification
project, you're looking to raise the degree of confidence in
your verification project, or if you're simply curious about
the roll of Functional Coverage in modern random-based
verification methods, then this course is for you.
This is an
interactive course with numerous individual and group labs that cement the concepts
taught in the lecture portion of each session. Students will
use the latest version of Verisity’s Specman Elite.
This class can be taught using
either Verilog or VHDL as the design language. You can sign-up
for or request a class that uses the HDL you prefer, although
little reference is made to the HDL model – part of the power
of Specman Elite.
You can
attend a regularly scheduled public course, or schedule your
own private session at your facility. To find out more,
contact us toll free now at ,
or contact us by
Clicking Here.
This course
is structured as multiple sessions taught over a 6 to 8 hour
period. Interactive labs and group exercises are distributed
throughout the course. For more information about course
content and structure, or if you're interested in
customization, please call us toll free at ,
or contact us by
Clicking Here.
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Section 1: |
Random-based Verification
Coverage |
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Review of the fundamentals of random-based verification |
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Generating tests with constraints |
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Self-checking with scoreboards and temporal checks |
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How coverage is integrated into the overall test
strategy |
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Section 2: |
The Role of the Verification
Plan |
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What is a Verification Plan
(VP)? |
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How VPs are created; issues of
ownership and format; common mistakes in VP structure. |
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The spiral process for
creating a VP. Hardware phases, verification
phases, random with phases. |
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Addressing on-the fly and
post-processing self-check strategies |
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Different aspect approaches to
verification, including interface-based, feature-based,
corner-based. Design for Verification approaches,
directed testcases, and the configuration generator
approach. |
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Section 3: |
Functional Coverage: How it
Works |
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The mechanics of coverage and
how it fits into the simulator and random-based
verification flow. |
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Functional coverage defined and where it takes you. |
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Setting coverage goals. |
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Group Exercise reviewing specification, VI
diagram, layers, phases, and aspects, with a full
example under review. |
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Section 4: |
Functional Coverage: Basic
Syntax |
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How coverage is enabled
(turned on and off) and the four coverage modes. |
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Coding guidelines for
coverage. |
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Setting up coverage groups (structs)
and selecting coverage options. |
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Determining when to sample data. |
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The three types of coverage items: basic, cross,
transition. How to define them and select cover
options and ranges. |
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Using coverage and configuring options. |
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Coverage I/O commands and how
to display (show) coverage data |
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Lab Session |
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Section 5: |
Functional Coverage:
Implementation |
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Implementing coverage via
extensions to simplify modification. |
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when vs. what:
thinking in terms of when to cover and what to cover. |
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Defining when:
establishing a point in time when sampled data is stable
and valid. Establishing coverage-specific events;
sampling, delayed clocks. Interface-based
coverage; Race conditions; Emit on what
computation; At generation; Hook methods; Handling
multiple struct instances. |
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Defining what:
the importance of sampling at the right level;
External coverage points. Timing and run
statistics. Defining what at generation
time. Defining coverage point fields. Internal
coverage points. On-the-fly coverage items.
Catching errors with the 'illegal' cover option. |
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Identifying holes in your
coverage: the importance of holes in identifying what
still needs to be done. Defining coverage goals,
evaluating cross-coverage reports. Setting number
of buckets, how to group values into buckets,
implications on memory usage. |
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Coverage reports, how they are
displayed (GUI, ASCII file), batching and merging
multiple runs into one file. Coverage grading. |
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Lab Session |
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Section 6: |
Coverage Concerns |
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Addressing verification system
performance. The impact of coding on
simulator/environment speed. The true cost of
coverage. Solutions for improving performance. |
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Dealing with data
overload -- what are you going to do with all of that
data? Intelligent data sampling to reduce data
load. |
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Minimizing memory usage,
profiling memory usage, garbage collection. |
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The role of incremental
coverage. |
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Lab Session:
Case study |
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There is no substitute for a private course
taught on-site at your facility, particularly when you have 6 or
more engineers to train. Simply put, for large groups it’s always
less expensive for us to come to you than the other way around. And
if you want a custom course, we can arrange it. Do you need to
squeeze a four day course into three? No problem. We know how to do
it without compromise. And if you need a course on short notice, we
can be there sooner than you think. For more information, contact us
at:
Verifica – the right kind of
verification training, tuned to your needs. Contact us now.
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