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Course duration: 3 days
This
three-day interactive course teaches you the basics of the e
language, the Specman Elite environment and the basic skills
you need to implement testbenches for complex ASIC, FPGA and
board-level designs. The course is rich in methodology hints
and tricks used by our verification experts who regularly
verify 10+ million gate systems. With the help and guidance of
our verification experts, you will learn:
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1. |
The introduction to e and Verisity’s Specman Elite
presents the tool, its interfaces, and its language.
This section explains why you would use Specman Elite
over an HDL and describes the relationship between
Specman Elite and your simulator. You see how to invoke
the tool and use the GUI. This section also gives you a
jump start on the most basic commands. |
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e
– The Language
describes structs, units and methods, and working with
data packets. |
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3. |
e
– The Language Actions
details the syntax and structure of the language in a
familiar single-thread, sequential environment similar
to C or PERL. This section also introduces an important
feature, unique to Verisity’s Specman Elite, that allows
existing code to be user-extended without modification.
In addition to learning how to extend structs, methods,
and types, you’ll learn about language actions. |
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4. |
The "spec" in Specman
Elite comes
from the ability to generate data values and sequences
that follow a set of constraints. This section presents
how your design specification is turned into a set of
constraints. Lists are introduced for the generation of
sequences and physical fields are used to map high-level
data types to bit-level data streams. The basic concepts
of automatic random data generation, object-oriented
data representation and inheritance are also presented. |
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The notion of time
in Specman Elite is introduced with the concept of
events. Events, coupled with temporal expressions and
time-consuming methods, can express the most complex
time-based relationships and bus-functional models. |
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6. |
Verifying your design
involves interfacing your Specman Elite testbench with
your Verilog or VHDL model. This section presents how to
access signals in the HDL simulation and how X's and Z's
are handled. Events and expects are used for verifying
the temporal dimension of your design's response. |
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7. |
Functional coverage
is an important concept that is well supported by
Verisity’s Specman Elite. Just as code coverage is used
to measure how well a testsuite executes the code of
your design, functional coverage is used to measure how
thoroughly a testsuite exercises your design. |
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8. |
Methodology guidelines
identifies key guidelines and steps through a complete
example to illustrate making the best use of Specman
Elite. |
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9. |
Miscellaneous utilities
introduces you to the built-in productivity-enhancing
features of Specman Elite and how to best implement a
verification environment with it. |
If you need
to verify a design with a high-degree of confidence using
Specman Elite, implement testbenches, and have little or no
prior knowledge of the fundamentals of e or Verisity’s
Specman Elite, then this course is for you.
This is an
interactive course with numerous labs that cement the concepts
taught in the lecture portion of each session. Students will
use the latest version of Verisity’s Specman Elite.
This class can be taught using
either Verilog or VHDL as the design language. Be sure you
sign-up for or request a class that uses the HDL you prefer.
You can
attend a regularly scheduled public course, or schedule your
own private session at your facility. To find out more,
contact us toll free now at ,
or contact us by
Clicking Here.
This course
is structured as multiple sessions taught over three days.
Interactive labs and group exercises are distributed
throughout the course. For more information about course
content and structure, or if you're interested in
customization, please call us toll free at ,
or contact us by
Clicking Here.
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Section 1: |
Specman Elite -- The Tool. |
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Why use a high-level verification language. Introduction
to the Specman Elite tool. The relationship between
Specman Elite and your simulator. |
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Lab Session |
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Section 2: |
e - The Language. |
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Syntax rules. Comments. Code hierarchy. |
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Structs and global structs. Predefined and enumerated
types. Lists and list indices. Units and using units and
structs. |
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Methods and using methods. Variables. Printing using the
out and print commands. |
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Lab Session |
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Section 3: |
e - The Language Actions. |
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Operator precedence. Controlling loops. Using actions.
Accessing HDL objects. |
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Extending types, lists, structs and methods. Inheritance
using conditional blocks and like. |
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Lab Session |
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Section 4: |
The "spec" in Specman. |
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Data generation and constraints. Hard and soft
constraints. Compound constraints. |
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List operators. Generating sequences using lists.
Implicit variables. |
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Lab Session |
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Physical data
fields versus logical data fields. Packing and
unpacking. |
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Lab Session |
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Section 5: |
The Notion of Time. |
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Declaring events. Temporal expressions and operators.
Evaluation of temporal expressions. |
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Time-consuming methods (TCMs). Invoking and
synchronizing TCMs. fork/join in Specman Elite. Modeling
state machines. |
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Synchronizing events with the HDL simulator. Events and
error checking. Predefined events. |
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Lab Session |
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Section 6: |
Verifying your Design |
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Working with Verilog (or VHDL). Attaching events to HDL
events. Referencing HDL signals. |
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Calling Verilog tasks (or VHDL procedures) from Specman
Elite. Specman Elite timescale. Using a waveform viewer.
Dealing with X's and Z's. |
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Switching between the Specman Elite and HDL simulation.
Saving and restarting. |
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Data checking. Using a reference model. Run-time
expected data generation. |
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Temporal checking. Expects. |
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Lab Session |
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Section 7: |
Functional Coverage |
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Definition of functional coverage. Functional coverage
versus code coverage. Functional coverage and the
verification plan. |
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Coverage groups and coverage commands. Incremental
coverage metrics. Reporting functional coverage metrics. |
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Lab Session |
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Section 8: |
Methodology Guidelines. |
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Structuring your verification environment. Verisity eRM
guidlelines. Configuration management. Directory
structure. File naming conventions. |
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Coding guidelines specific to Specman Elite.
Initializing testcases. Run-time generation. |
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Writing a verification plan. Implementing your
verification plan. Constraint-driven random
verification. Feedback from functional coverage.
Self-checking strategies. Regressions. |
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Compiled versus interpreted simulation. |
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A complete example highlighting how to best use Specman
Elite. Reviews the design, testbenches, models,
coverage, and injecting errors. Runs the example at
these and other key steps. |
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Lab Session |
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Section 9: |
Miscelaneous Utilities |
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Pattern matching and other string operators. File I/O.
Interfacing to a subshell. Defining macros to extend the
language. |
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Lab Session |
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There is no substitute for a private course
taught on-site at your facility, particularly when you have 6 or
more engineers to train. Simply put, for large groups it’s always
less expensive for us to come to you than the other way around. And
if you want a custom course, we can arrange it. Do you need to
squeeze a four day course into three? No problem. We know how to do
it without compromise. And if you need a course on short notice, we
can be there sooner than you think. For more information, contact us
at:
Verifica – the right kind of
verification training, tuned to your needs. Contact us now.
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