Verifica Course: Advanced Verification Methods Using Vera

Advanced Verification Methods Using VERA
Including Synopsys RVM^TM

Course duration: 3 days

Course Curriculum.

This three-day interactive course teaches you how to overcome the "white page syndrome" – Now that you know Synopsys VERA, what’s next? In this class, you will go through the step-by-step process required to plan and implement a sophisticated, self-checking verification environment for first-time success.

The course is rich in methodology hints and tricks used by our verification experts who regularly verify 10+ million gate systems – experts with knowledge that only comes from being the independent voice in the EDA verification industry. With the help and guidance of our experienced VERA verification consultants, you will learn:

	1.	Jump Start Vera review refreshes your mind about key concepts in using Vera to verify your designs. This review reminds you about important concepts, reinterates helpful tips and methodology you may have overlooked, and ensures everyone is familiar with the elements that are used throughout the course.
	2.	Data modeling helps you understand how to model data objects. Object oriented thinking is presented in the verification context and example data structures are discussed. Implementation techniques for properly translated high-level data types to physical levels are demonstrated.
	3.	Verifcation strategy first demonstrates how random, constrained testing can be more productive than a traditional, directed testing approach. Next, the role of functional coverage as a constrained-random approach is explored. Lastly, the details of how to implement the appropriate constrainable, random environment structure for the verification strategy you have outlined.
	4.	Bus functional models are the cornerstone of a proper high-level verification process. When properly designed, they can be highly reusable and configurable.
	5.	Implementing the environment identifies that a constrained-random approach requires a different implementation then a directed approach. A process for defining a suitable plan is presented.
	6.	Random generation involves more then calling a random number generator function. Random generation must be properly designed to offer the a level of controllability over all significant parameters, while minimizing the modifications necessary to add or tune constraints. Random generation will also be used to inject errors or protocol violations in bus functional models.
	7.	Functional coverage answers the question of how much work is left? This section explores in details what needs to be verified and when to do it.
	8.	Synopsys RVM overview thoroughly explains the Synopsys-recommended Reference Verification Methodology (RVM) and the benefits of using standardized data and transaction models, message service, transactor models and verification environment simulation flow.
	9.	Protocol-based verification self-checking strategy characteristics are identified. A scoreboarding strategy using Synopsys RVM is examined in-depth.
	10.	Simulation management (optional) explains how the simulations are carried out. Configuration management, directory structure and scripts are discussed The merits of using tracing and logging are explained.

Who should attend?

If you need to verify a design with a high-degree of confidence, implement testbenches creating reusable verification components, minimize code development effort, increase productivity and have little or some prior knowledge of the fundamentals of Synopsys VERA, then this course is for you.

The learning environment.

This is an interactive course with numerous labs that cement the concepts taught in the lecture portion of each session. Students will use the latest version of Synopsys VERA and VCS.

How to attend this course.

You can attend a regularly scheduled public course, or schedule your own private session at your facility. To find out more, contact us toll free now at , or contact us by Clicking Here.

Detailed course outline.

This course is structured as multiple sessions taught over three days. Interactive labs and group exercises are distributed throughout the course. For more information about course content and structure, or if you're interested in customization, please call us toll free at , or contact us by Clicking Here.

	Section 1:	Jump Start Vera Language Refresher
		Review of key Vera constructs.
		Working with the verification "big picture" in mind.
		Verification strategy flow.
		*Lab Session*

	Section 2:	Data Modeling
		Example data structures, including packets; instructions, transactions; BFMs; and configuration descriptors.
		Constructors, including layering techniques and initializing data.
		Physical vs. virtual fields
		Planning inheritance, including virtual classes and methods
		Customizing packing/unpacking
		How to map data structures into another; example of mapping TCP/IP packets onto a MAC frame; how to add information to a RAW payload.
		Handling *.vrh files, including old vs. new files
		The list macro, including usage; the list macro vs. associated arrays
		*Lab Session*

	Section 3:	Verification Strategy
		Random + constraints + item coverage; cross coverage and adding constraints
		Strategy for system vs. ASIC vs. block verification.
		Handling interfaces
		Strategies for error detection.
		Structuring the environment.
		Handling termination conditions.
		*Lab Session*

	Section 4:	Bus-Functional Models
		Usage model issues, including: procedural interfaces; queues and TCMs; the difference between TCMs and non-TCMs; how to start and reset processes.
		Using virtual ports as an integration mechanism; separating timing from function; creating delay models; handling asynchronous interfaces; pass bind in constructor.
		User extension mechanisms, including derivatives and callback class
		Handling *.vrh files, old vs. new files.
		*Lab Session*

	Section 5:	Implementing the Environment
		The implementation process
		Data, protocol, and whitebox checking.
		Functional coverage points.
		Directed testcases.
		Design for verification issues
		*Lab Session*

	Section 6:	Random Generation Strategy
		Constraining discrete data items
		Constraining discrete channels/instances.
		Dynamic constraint controls
		Stream generation, including strategies for generating valid sequences and random-length sequences
		Constraint management, including using randomize() with; using "weights" field; using dynamic control; using external definitions.
		*Lab Session*
		Strategies for error injection.
		Writing and managing temporal expressions
		*Lab Session*
		Seed management, including using local random sources
		How to reproduce results (repeatability issues)

	Section 7:	Functional Coverage
		When vs. what; defining when and handling race conditions. Defining what on a per-instance basis, and for all instances.
		Defining coverage goals.
		Generating coverage reports, interpretations, and the limitations on cross-coverage.
		Managing coverage control, including turning coverage on and off, incremental coverage, and handling name uniqueness (per seed/test).
		*Lab Session*

	Section 8:	Synopsys Reference Verification Methodology (RVM)
		Coding and Compilation, including RVM declarations, implementations and directives. Specific coding guidelines for code reuse
		Testbench architectures including coverage-driven verification, layered models and managing different layers
		Using the Common Message Service, rvm_log, rvm_log_msg
		Data and transaction model recommendations, including properties, data members, methods, constraints, and the test configuration descriptor; rvm_data, rvm_channel, rvm_broadcast
		Transactors and recommended models including completion and response models, in-order atomic execution model. Handling out-of-order execution, concurrent, split or recurring transaction execution. rvm_xactor
		*Lab Session*
		Managing stimulus generation and events, and using various generator types including atomic, scenario, directed and embedded generators. rvm_scheduler, rvm_notify, rvm_notify_event, rvm_scenario_gen, rvm_atomic_gen
		Managing the verification environment simulation flow, handling compilation dependencies. rvm_env, rvm_watchdog
		Managing testcases, including concatenating testcases, adding directed stimulus, and injecting errors.
		*Lab Session*

	Section 9:	Self-Checking of Protocol-based Systems
		Characteristics of protocol-based designs.
		Creating scoreboards for protocol-based systems
		Checking strategies for protocol-based systems
		*Lab Session*

	Section 10:	Simulation Management (optional)
		Managing test environment configurations, including Makefiles, .vrl files, and .proj files.
		Tracing and logging, including post-run checking and issues on name uniqueness (per seed/test)
		*Lab Session*

Schedule your Verifica course today.

There is no substitute for a private course taught on-site at your facility, particularly when you have 6 or more engineers to train. Simply put, for large groups it’s always less expensive for us to come to you than the other way around. And if you want a custom course, we can arrange it. Do you need to squeeze a four day course into three? No problem. We know how to do it without compromise. And if you need a course on short notice, we can be there sooner than you think. For more information, contact us at:

Verifica – the right kind of verification training, tuned to your needs. Contact us now.