Verifica Course: Advanced Verification Methods Using Verilog

Advanced Verification Methods Using Verilog

Course duration: 3 days

Course Curriculum.

This three-day interactive course teaches you how to overcome the "white page syndrome" – Now that you know Verilog, what’s next? In this class, you will go through the step-by-step process required to plan and implement a sophisticated, self-checking verification environment for first-time success.

The course is rich in methodology hints and tricks used by our verification experts who regularly verify 10+ million gate systems – experts with knowledge that only comes from being the independent voice in the EDA verification industry. With the help and guidance of our experienced Verilog verification consultants, you will learn:

	1.	The basics of writing testbenches presents how functional verification fits into the overall design process. The experienced RTL designer or Verilog novice is then introduced to the concepts of applying stimulus and observing response in a more sophisticated fashion than using simple synchronous test vectors.
	2.	Advanced behavioral modeling techniques introduces unsynthesizable language constructs that are indispensable when writing testbenches. Techniques for packaging bus-functional models to make them easy to reuse across different testbenches are presented. Defensive modeling techniques are shown: they help reduce debug time and enhance the portability of the Verilog code.
	3.	Advanced verification techniques are presented to minimize maintenance and code duplication between numerous testbenches. Complex verification sequences are decomposed into high- and mid-level service procedures on top of the low-level procedural interface provided by the bus-functional models. The techniques for properly writing a pin-accurate full-functional behavioral model are presented. When properly written, a behavioral model is not even close to a RTL model, and simulates 10 to 100 times faster.
	4.	Verilog Expert Topics, we answer the frequently asked questions from thousands of students and show you the lesser known techniques that save you real project time.

Who should attend?

If you need to verify a design with a high-degree of confidence, implement testbenches creating reusable verification components, minimize code development effort, increase productivity and have little or some prior knowledge of the fundamentals of e or Specman Elite, then this course is for you.

Prerequisites for this class.

Successful completion of Verifica’s course Introduction to Verilog Verification Methods or equivalent experience with Verilog.

The learning environment.

This is an interactive course with numerous labs that cement the concepts taught in the lecture portion of each session. In our public courses, you may choose from Synopsys VCS or Model Technology ModelSim as your simulator for labs. For private on-site classes, you may use the design environment of your choice: Cadence Incisive platform or NC-Verilog, Synopsys VCS, or Model Technology ModelSim. SignalScan or Undertow can also be used to view waveforms.

How to attend this course.

You can attend a regularly scheduled public course, or schedule your own private session at your facility. To find out more, contact us toll free now at , or contact us by Clicking Here.

Detailed course outline.

This course is structured as multiple sessions taught over three days. Interactive labs and group exercises are distributed throughout the course. For more information about course content and structure, or if you're interested in customization, please call us toll free at , or contact us by Clicking Here.

	Section 1:	Introduction to Testbenches
		Functional verification in the overall design process. How does it differ from formal verification or hardware testing? How do you make sure that you verify against the design intent?
		File input and output. How to report and display simulation results. How to write programmable testbenches.
		*Lab Session*
		How to apply stimulus using behavioral constructs. Reporting results in a meaningful way. Avoiding having to look at waveforms.
		*Lab Session*
		How to abstract operations using bus-functional models. Embedded output validation in a self-checking bus-functional model.
		*Lab Session*
		Bus-functional models for CPU buses and interfaces. How to model an asynchronous protocol and return data uninterpreted.
		*Lab Session*
		Adding observability inside a model and white-box verification. Hierarchical references.
		*Lab Session*
		Full-timing gate-level simulation with SDF back-annotation.
		*Lab Session*

	Section 2:	Advanced Modeling Techniques
		Specification of a design that needs to be verified.
		*Lab Session: design a verification plan*
		Modeling asynchronous protocols and timing checks. The disable statement and named blocks. The fork/join statement. Local declarations.
		*Lab Session*
		Parameters compared to `defined symbols. A set of tasks implementing a complete bus-functional model for a CPU. Defensive modeling techniques. Preventing the simulation from hanging up forever.
		*Lab Session*
		Concurrent task activation. Packaging tasks to facilitate distribution and reuse.
		*Lab Session*
		Detecting and reporting concurrent task activation. Defensive modeling techniques for packaged bus-functional models.
		*Lab Session*
		Writing configurable bus-functional models. Emulating an enumerated type for symbolic values.
		*Lab Session*
		Slave bus-functional models. Timing restrictions imposed by them. Making sure no data is missed by slave models.
		*Lab Session*

	Section 3:	Advanced Verification Techniques
		Creating a functional verification infrastructure to minimize maintenance and duplicated code across several testbenches.
		*Lab Session*
		Layering verification services into high- and mid-level service tasks on top of the low-level procedural interfaces provided by the bus-functional models. Writing a task verifying an arbitrary memory-mapped register and describing the characteristics of a particular registers. Implementing the testcase verifying the correct implementation of the memory-mapped register interface.
		*Lab Session*
		Verifying the data transmission capabilities of the design. Verifying all possible configurations of a design. Stressing the design at maximum speed. Eliminating wait states created by output checking.
		*Lab Session*
		The benefits of behavioral models. The characteristics of a properly written behavioral models. Avoiding the RTL mindset when writing a verification model. Modeling techniques for memory-mapped registers.
		*Lab Session*
		Bus-functional models as part of behavioral verification models. Tying multiple interfaces together in a behavioral model. Writing a full-functional behavioral model.
		*Lab Session*

	Section 4:	Verilog Expert Topics
		What they did not teach you in your last Verilog class: portability issues in Verilog code. How to make sure your model works on any Verilog simulator using any command-line options.
		Race conditions. Execution order at simulation startup Unspecified behavior in the IEEE standard Pin directions Resolving hierarchical names
		What is the synthesis subset. Partitioning and describing combinational and sequential functions. Inferring flip-flops and describing FSMs. Coding style issues.
		Modeling clock generators. Aligning events in synchronized clocks: how to deal with simulation events skew.
		A real-life example of misunderstanding how the non-blocking and blocking assignments work.
		Modeling ROMs. Synthesis considerations. Simulation efficiency considerations for functional verification.

Schedule your Verifica course today.

There is no substitute for a private course taught on-site at your facility, particularly when you have 6 or more engineers to train. Simply put, for large groups it’s always less expensive for us to come to you than the other way around. And if you want a custom course, we can arrange it. Do you need to squeeze a four day course into three? No problem. We know how to do it without compromise. And if you need a course on short notice, we can be there sooner than you think. For more information, contact us at:

Verifica – the right kind of verification training, tuned to your needs. Contact us now.