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Course duration: 3 days
This
three-day interactive course teaches you the basics of the
Verilog language, the tool environment, and the basic skills
you need to implement testbenches for complex ASIC, FPGA and
board-level designs. The course is rich in methodology hints
and tricks used by our verification experts who regularly
verify 10+ million gate systems. With the help and guidance of
our verification experts, you will learn:
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1. |
Verilog as a sequential language introduces the
syntax and structure of the language in a familiar
single-thread, sequential environment similar to C or
PERL. |
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2. |
Verilog concurrency
constructs
provide the features that make hardware description
languages different from ordinary general purpose
programming languages: time and parallelism. |
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3. |
Verilog structural
constructs
provide another feature that makes hardware description
languages different from ordinary general purpose
programming languages: structural decomposition. |
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The basics of writing
testbenches
presents how functional verification fits into the
overall design process. The experienced RTL designer or
Verilog novice is then introduced to the concepts of
applying stimulus and observing response in a more
sophisticated fashion than using simple synchronous test
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If you need
to verify a design with a high-degree of confidence, write a
test plan, or implement testbenches in Verilog, and have
little to no prior knowledge of Verilog, then this course is
ideal for you.
This is an
interactive course with numerous labs that cement the concepts
taught in the lecture portion of each session. In our public
courses, you may choose from Synopsys VCS or Model Technology
ModelSim as your simulator for labs. For private on-site
classes, you may use the design environment of your choice:
Cadence Incisive platform or NC-Verilog, Synopsys VCS, or
Model Technology ModelSim. SignalScan or Undertow can also be
used to view waveforms.
You can
attend a regularly scheduled public course, or schedule your
own private session at your facility. To find out more,
contact us toll free now at ,
or contact us by
Clicking Here.
This course
is structured as multiple sessions taught over three days.
Interactive labs and group exercises are distributed
throughout the course. For more information about course
content and structure, or if you're interested in
customization, please call us toll free at ,
or contact us by
Clicking Here.
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Section 1: |
Verilog as a Sequential
Language |
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The basic compilation unit: modules. Syntax rules for
user-defined identifiers and reserved words. Source file
requirements and compiling a Verilog model. |
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Lab Session |
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The always and initial blocks and sequential statements.
The $write statement. Terminating the simulation. |
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Lab Session |
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Declaring and using registers and memories. Values,
operators, and expressions. |
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Lab Session |
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Control-flow statements. |
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Lab Session |
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Functions and tasks. Calling functions and tasks. |
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Lab Session |
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Section 2: |
Verilog as a Parallel
Language |
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Procedural blocks as the units of parallelism. The @, #,
and wait statements. The delayed blocking assignment. |
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Lab session. |
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Event-driven simulation and the simulation cycle. |
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Lab Session |
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Race conditions created by the blocking assignment. The
non-blocking assignment and the event queue. The
transport delay model. |
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Lab Session |
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The concept of drivers and wires. The continuous
assignment. Drive strengths. The inertial delay model.
Drivers on wires compared to assignments to registers. |
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Lab Session |
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Section 3: |
Verilog as a Structural
Language. |
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The hierarchical decomposition process. Pins on modules.
Connecting and driving pins. Instantiating modules. |
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Lab Session |
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Parameters. Using parameters to specify
instance-specific timing values. Using parameters to
specify variable width designs. |
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Lab Session |
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The timescale directive. The impact of resolution and
precision. Predefined time-related tasks and functions. |
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Lab Session |
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Simulation and configuration management. |
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Lab Session |
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Section 4: |
Introduction to Testbenches |
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Functional verification in the overall design process.
How does it differ from formal verification or hardware
testing? How do you make sure that you verify against
the design intent? |
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File input and
output. How to report and display simulation results.
How to write programmable testbenches. |
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Lab Session |
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How
to apply stimulus using behavioral constructs. Reporting
results in a meaningful way. Avoiding having to look at
waveforms. |
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Lab Session |
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How to abstract operations using bus-functional models.
Embedded output validation in a self-checking
bus-functional model. |
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Lab Session |
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Bus-functional models for CPU buses and interfaces. How
to model an asynchronous protocol and return data
uninterpreted. |
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Lab Session |
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Adding observability inside a model and white-box
verification. Hierarchical references. |
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Lab Session |
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Full-timing gate-level simulation with SDF
back-annotation. |
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Lab Session |
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There is no substitute for a private course
taught on-site at your facility, particularly when you have 6 or
more engineers to train. Simply put, for large groups it’s always
less expensive for us to come to you than the other way around. And
if you want a custom course, we can arrange it. Do you need to
squeeze a four day course into three? No problem. We know how to do
it without compromise. And if you need a course on short notice, we
can be there sooner than you think. For more information, contact us
at:
Verifica – the right kind of
verification training, tuned to your needs. Contact us now.
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