|
Course duration: 3 days
This
three-day interactive course teaches you how to overcome the
"white page syndrome" – Now that you know VHDL, what’s next?
In this class, you will go through the step-by-step process
required to plan and implement a sophisticated, self-checking
verification environment for first-time success.
The course is rich in
methodology hints and tricks used by our verification experts
who regularly verify 10+ million gate systems – experts with
knowledge that only comes from being the independent
voice in the EDA verification industry. With the help and
guidance of our experienced VHDL verification consultants, you
will learn:
| |
1. |
The basics of writing testbenches presents how
functional verification fits into the overall design
process. The experienced RTL designer or VHDL novice is
then introduced to the concepts of applying stimulus and
observing response in a more sophisticated fashion than
using simple synchronous test vectors. |
|
|
2. |
User-defined types,
usually not synthesizable, are very powerful for writing
testbenches. Enumerated types, records, and arrays, as
well as subtypes constraining them are covered. Packages
are introduced as the mechanism to share and distribute
type declaration and their associated subprograms. |
| |
3. |
Advanced verification
techniques are
presented to minimize maintenance and code duplication
between numerous testbenches. Complex verification
sequences are decomposed into high- and mid-level
service procedures on top of the low-level procedural
interface provided by the bus-functional models. |
| |
4. |
The advanced language
features
offered by access types, generate statements and
concurrent procedure calls create opportunities for
writing more efficient verification structures. Access
types and linked lists can be used to efficiently model
large memories, while generate statements can be used to
easily describe regular structures. |
If you need
to verify a design with a high-degree of confidence, write a
test plan, or implement testbenches in VHDL, then this course
is for you. Because of the advanced nature of this course,
you must have prior knowledge of the fundamentals of VHDL
before attending this course.
Successful
completion of Verifica’s course
Introduction to
VHDL Verification Methods
or equivalent experience with VHDL.
This is an
interactive course with numerous labs that cement the concepts
taught in the lecture portion of each session. Students will
use their choice of the latest version of VHDL simulators from
Synopsys (VCS MX), Cadence (Incisive and NC-VHDL), and Mentor
Graphics (ModelSim).
You can
attend a regularly scheduled public course, or schedule your
own private session at your facility. To find out more,
contact us toll free now at ,
or contact us by
Clicking Here.
This course
is structured as multiple sessions taught over three days.
Interactive labs and group exercises are distributed
throughout the course. For more information about course
content and structure, or if you're interested in
customization, please call us toll free at ,
or contact us by
Clicking Here.
| |
Section 1: |
Introduction to Testbenches |
| |
 |
Functional verification in
the overall design process. How does it differ from
formal verification or hardware testing? How do you make
sure that you verify against the design intent? |
| |
|
VHDL libraries |
| |
|
-
How to configure your VHDL
tools to understand where a particular library is
located.
-
Referencing library units
in other libraries.
-
Structuring your model
across multiple libraries.
|
| |
|
Lab Session |
| |
|
File input using TEXTIO.
How to write programmable testbenches. |
| |
|
Lab Session |
| |
|
How to abstract operations
using bus-functional models. Embedded output validation
in a self-checking bus-functional model. |
| |
|
Lab Session |
| |
|
Bus-functional models for
CPU buses and interfaces. How to model an asynchronous
protocol and return data uninterpreted. |
| |
|
Lab Session |
| |
|
Turning a testbench into a
component of a regression suite. How to write a
testbench tolerant of changes in latency, throughput or
clock cycle boundaries. Adding observability inside a
model and white-box verification. |
| |
|
Lab Session |
| |
|
|
| |
Section 2: |
User-Defined Types |
| |
|
Enumerated types: how to define them and how to use
them. What are they useful for? Overloading an enumeral.
Using a subtype to constrain the range of a enumerated
type. Predefined enumerated types. |
| |
|
Lab Session |
| |
|
Defining unconstrained and multi-dimensional arrays.
Array attributes and literals. Using an enumerated type
to index an array. Defining standard array sizes using
subtypes. |
| |
|
Lab Session |
| |
|
Using record to keep related information of different
types together. How to declare and use a record type.
Record literals or aggregates. Comparing records and
arrays. |
| |
|
Lab Session |
| |
|
Overloading functions and procedures to enhance
readability and conserve the name space. Publishing and
sharing useful types and subprograms using packages.
Dependencies on package and their bodies. Predefined
packages. |
| |
|
Lab Session |
| |
|
|
| |
Section 3: |
Advanced Verification
Techniques |
| |
|
Specification of a design that needs to be verified. |
| |
|
Lab Session: design
a verification plan |
| |
|
Modeling asynchronous
protocols and verifying that timing constraints are met.
Indicating completion status and error recovery. |
| |
|
Lab Session |
| |
|
Assigning signals in a
procedure via side-effects. Implied signal drivers and
restrictions on locating the procedure declaration.
Arguments of kind signal and distributing bus-functional
models in packages. |
| |
|
Lab Session |
| |
|
Handling exceptions such
as reset. Aborting a bus-functional procedure. |
| |
|
Lab Session |
| |
|
A complete set of
procedures implementing a bus-functional model for a CPU
interface. |
| |
|
Lab Session |
| |
|
Writing an initialization
procedure to minimize the amount of duplicated code
between different testbenches. |
| |
|
Lab Session |
| |
|
Writing a procedure
verifying an arbitrary memory-mapped register and
describing the characteristics of a particular
registers. Dealing with unpredictable or incompatible
array bounds in unconstrained formal subprogram
arguments. |
| |
|
Lab Session |
| |
|
Implementing the testcase
verifying the correct implementation of the
memory-mapped register interface. How to use strong
typing to your advantage: choosing the appropriate data
types to minimize the probability of run-time errors. |
| |
|
Lab Session |
| |
|
Writing a configurable
bus-functional model. Choosing the appropriate data
types to represent configuration data. Verifying the
data transmission capabilities of the design. |
| |
|
Lab Session |
| |
|
Stressing the design at
maximum speed. Eliminating wait states created by output
checking. Implementing a fork/join control structure. |
| |
|
Lab Session |
| |
|
Timing restrictions
imposed by slave bus-functional models. Ensuring that no
data is missed by a slave model. |
| |
|
Lab Session |
| |
|
|
| |
Section 4: |
Advanced Language Constructs |
| |
|
Access types: pointers in VHDL. Allocating, accessing,
then de-allocating dynamic memory. Using access types to
implement a linked list to model a large memory |
| |
|
Lab Session |
| |
|
Using concurrent procedure calls to implement small
single-process entity/architectures without the
additional overhead of additional library units, a
component declaration and a configuration statement.
|
| |
|
Lab Session |
| |
|
Using the if-generate
statement to create models with optional behavior. The
difference between if-generate statements and ifdef
preprocessor directives. Recursive hardware models.
Describing regular, repetitive structures using the
for-generate statement. Generate statements and
unconstrained ports. Configuring instantiations inside
generate statements. |
| |
|
Lab Session |
| |
|
Debugging contradictions. |
| |
|
Lab Session |
| |
|
|
There is no substitute for a private course
taught on-site at your facility, particularly when you have 6 or
more engineers to train. Simply put, for large groups it’s always
less expensive for us to come to you than the other way around. And
if you want a custom course, we can arrange it. Do you need to
squeeze a four day course into three? No problem. We know how to do
it without compromise. And if you need a course on short notice, we
can be there sooner than you think. For more information, contact us
at:
Verifica – the right kind of
verification training, tuned to your needs. Contact us now.
|
|
