Verifica Course: Introduction to VHDL Verification Methods

Introduction to VHDL Verification Methods

Course duration: 3 days

Course Curriculum.

This three-day interactive course teaches you the basics of the VHDL language, the tool environment, and the basic skills you need to implement testbenches for complex ASIC, FPGA and board-level designs. The course is rich in methodology hints and tricks used by our verification experts who regularly verify 10+ million gate systems. With the help and guidance of our verification experts, you will learn::

	1.	VHDL as a sequential language introduces the syntax and structure of the language in a familiar single-thread, sequential environment similar to C or PERL.
	2.	VHDL concurrency constructs provide the features that make hardware description languages different from ordinary general purpose programming language: time, parallelism, and structure.
	3.	The basics of writing testbenches presents how functional verification fits into the overall design process. The experienced RTL designer or VHDL novice is then introduced to the concepts of applying stimulus and observing response in a more sophisticated fashion than using simple synchronous test vectors.

Who should attend?

If you need to verify a design with a high-degree of confidence, write a test plan, or implement testbenches in VHDL, and have little to no prior knowledge of VHDL, then this course is ideal for you.

The learning environment.

This is an interactive course with numerous labs that cement the concepts taught in the lecture portion of each session. Students will use their choice of the latest version of VHDL simulators from Synopsys (VCS MX), Cadence (Incisive and NC-VHDL), and Mentor Graphics (ModelSim).

How to attend this course.

You can attend a regularly scheduled public course, or schedule your own private session at your facility. To find out more, contact us toll free now at , or contact us by Clicking Here.

Detailed course outline.

This course is structured as multiple sessions taught over three days. Interactive labs and group exercises are distributed throughout the course. For more information about course content and structure, or if you're interested in customization, please call us toll free at , or contact us by Clicking Here.

	Section 1:	VHDL as a Sequential Language
		Basic compilation units: entities and architectures. Syntax rules for user-defined identifiers and reserved words. Compiling a VHDL model and compilation dependencies. Simulating a VHDL model.
		*Lab Session*
		The process statement and sequential statements. The assert statement. Terminating the simulation.
		*Lab Session*
		Declaring constants and variables. Predefined types and operators. Control-flow statements.
		*Lab Session*
		Functions and procedures. Calling functions and procedures. Predefined functions.
		*Lab Session*
		Displaying formatted messages using TEXTIO.
		*Lab Session*

	Section 2:	VHDL as a Parallel Language
		Event-driven simulation and the simulation cycle. Processes as the units of parallelism and how everything is a process. Communicating between processes using signals. Sensitivity list and the wait statement. Predefined type TIME and NOW function.
		*Lab Session*
		The inertial and transport delay models and signal event queues. Using the appropriate sensitivity and delay model. Interesting attributes on signals and timing checks.
		*Lab Session*
		The concept of drivers and resolution functions. Drivers compared to assignments.
		*Lab Session*
		Ports on entities and instantiations. Declaring, instantiating and configuring components. Default configuration and configuration units.
		*Lab Session*

	Section 3:	Introduction to Testbenches
		Functional verification in the overall design process. How does it differ from formal verification or hardware testing? How do you make sure that you verify against the design intent?
		VHDL libraries
		How to configure your VHDL tools to understand where a particular library is located. Referencing library units in other libraries Structuring your model across multiple libraries
		*Lab Session*
		File input using TEXTIO. How to write programmable testbenches.
		*Lab Session*
		How to abstract operations using bus-functional models. Embedded output validation in a self-checking bus-functional model.
		*Lab Session*
		Bus-functional models for CPU buses and interfaces. How to model an asynchronous protocol and return data uninterpreted.
		*Lab Session*
		Turning a testbench into a component of a regression suite. How to write a testbench tolerant of changes in latency, throughput or clock cycle boundaries. Adding observability inside a model and white-box verification.
		*Lab Session*

Schedule your Verifica course today.

There is no substitute for a private course taught on-site at your facility, particularly when you have 6 or more engineers to train. Simply put, for large groups it’s always less expensive for us to come to you than the other way around. And if you want a custom course, we can arrange it. Do you need to squeeze a four day course into three? No problem. We know how to do it without compromise. And if you need a course on short notice, we can be there sooner than you think. For more information, contact us at:

Verifica – the right kind of verification training, tuned to your needs. Contact us now.